1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly, to an improvement of an arrangement of pads on a semiconductor chip.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as a "DRAM") is one of semiconductor integrated circuit devices which are produced relatively in large quantity. Table 1 shows one example of items of a 64-mega bit DRAM.
TABLE 1 ______________________________________ Word con- figuration x1 x4 x8 x16 ______________________________________ Operation Fast page Fast page Fast page 1 CAS 2 CAS mode Static Static Static 2 WE 1 WE column column column Fast page Fast page Nibble Nibble Static Static column column ______________________________________
As is shown in Table 1, the word configuration includes a "x1 configuration", a "x4 configuration", a "x8 configuration", and a "x16 configuration". The operation mode corresponding to the "x1 configuration" includes a "fast page mode", a "static column mode", and a "nibble mode". The operation mode corresponding to the "x4 configuration" includes the same modes as those corresponding to the "x1 configuration". The operation mode corresponding to the "x8 configuration" includes the "fast page mode" and the "static column mode". The operation mode corresponding to the "x16 configuration" includes a mode having one column address strobe signal (CAS) and two write enable signals (WE), and a mode having two column address strobe signals (CAS) and one write enable signal (WE). Each of the modes further includes the "fast page mode", and the "static column mode".
These items are identical to each other in the center portion such as a memory cell, and only different from each other in a part of the peripheral circuit. Therefore, item-by-item development thereof is not economical.
A method is employed of producing respective items by mounting a circuit having a plurality of functions on a semiconductor chip and switching the circuit. A method of switching includes a method of switching the circuit by changing patterning of an interconnection layer, and a method of switching the circuit by wire bonding.
FIG. 15 is a plan view showing a part of a conventional semiconductor integrated circuit device in which items are switched by bonding. Referring to FIG. 15, a plurality of leads 3 are disposed on a semiconductor chip 2. These leads 3 project outside through a package (not shown) housing semiconductor chip 2. The projected portions configure external pins of the semiconductor integrated circuit device. Such a configuration in which leads 3 are disposed on semiconductor chip 2 is called LOC (Lead On Chip).
A plurality of power supply pads 4 are arranged on semiconductor chip 2. Respective power supply pads 4 are connected to power supply leads 3 to which power supply potential Vcc or Vss is applied via wires 5. These wires 5 are formed by bonding.
Two selection pads MS1, MS2 are disposed adjacent to power supply pads 4 on semiconductor chip 2. By connecting these selection pads MS1, MS2 to corresponding power supply leads 3 via wires 5 or not, items are switched.
FIG. 16 is a selecting circuit shown in FIG. 2, page 5-267 of Vol. 5, Articles of Spring Seminar, Institute of Electronics, Information and Communication Engineers of Japan, 1993. Referring to FIG. 16, when selection pad MS1 is connected to power supply lead 3 to which ground potential Vss is applied, the potential of selection pad MS1 attains ground potential Vss. As a result, an L (logic low) level corresponding to ground potential Vss is output through two series connected inverters 704, 706. Therefore, in this case, an internal mode select signal MSI at an L level is provided.
On the other hand, when selection pad MS1 is not connected to any leads, the potential of selection pad MS1 is pulled up to power supply potential Vcc by a P channel MOS transistor 702. As a result, an H (logic high) level corresponding to power supply potential Vcc is output through two inverters 704, 706. Therefore, in this case, mode select signal MSI attains an H level.
As described above, selection pad MS1 has either a connection state to power supply lead 3 or a disconnection state therefrom, and selection pad MS2 also has either a connection state to power supply lead 3 or a disconnection state therefrom. Therefore, switching among four items can be carried out depending on whether selection pads MS1, MS2 are connected to power supply leads 3 or not.
In a conventional semiconductor integrated circuit device, however, there was a case where two selection pads MS1, MS2 are both connected to one power supply lead 3, as shown in FIG. 15. Bonding of a plurality of wires 5 to one power supply lead 3 has the following problems.
First, when the first wire 5 is bonded and then second wire 5 is bonded, the second wire must be bonded at a position different from a position of bonding of the first wire. This is because bonding of the second wire 5 at the same position as that of the first wire decouples or disconnects the first wire 5 by the shock. Therefore, the width of lead 3 must be relatively wide. However, since lead 3 must be spaced from its adjacent lead, the width of lead 3 cannot be extremely increased.
Second, semiconductor chip 2 is damaged at the time of bonding. FIG. 17 is a side view showing the relationship between semiconductor chip 2 and lead 3 shown in FIG. 15. As is indicated by a dotted line in FIG. 17, lead 3 is bent by a bonding arm 9 at the time of bonding, which sometimes brings the tip of lead 3 into contact with the surface of semiconductor chip 2. If bonding is carried out to one lead 3 a plurality of times, the same place on semiconductor chip 2 is repeatedly subjected to damage. Lead 3 is also subjected to damage repeatedly. Therefore, it is desired that the number of times of bonding to one lead 3 is smaller.
It should be noted that there is a product called reverse bend other than items shown in Table 1. The reverse bend product has a pin arrangement in symmetry with respect to that of a normal product, that is, a normal bend product (non-reverse bend product). By packaging a normal bend product in the front side of a double sided printed circuit board and a reverse bend product in the rear side thereof, respective pins of the normal bend product can be connected to corresponding pins of the reverse bend product.
These normal and reverse bend products can be produced by bending lead 3 to the lower side or to the upper side in the figure after molding semiconductor chip 2 by a package 1, as shown in the right side of FIG. 18. When such a method is employed, lead 3 must be disposed at the center C in the thickness direction of package 1. However, as shown in the left side of FIG. 18, it is difficult to dispose lead 3 at the center C in the case of a package of an LOC type. Similarly, it is difficult to dispose lead 3 at the center C in the case of a super thin package called TSOP. If lead 3 cannot be disposed at the center in the thickness direction of package 1, the shape of lead 3 is different between the normal bend product and the reverse bend product.